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영문 논문지

홈 홈 > 연구문헌 > 영문 논문지 > IEIE Transactions on Smart Processing & Computing (IEIE SPC)

IEIE Transactions on Smart Processing & Computing (IEIE SPC)

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한글제목(Korean Title) Real-time Speed Limit Traffic Sign Detection System for Robust Automotive Environments
영문제목(English Title) Real-time Speed Limit Traffic Sign Detection System for Robust Automotive Environments
저자(Author) Anh-Tuan Hoang   Tetsushi Koide   Masaharu Yamamoto  
원문수록처(Citation) VOL 04 NO. 04 PP. 0237 ~ 0250 (2015. 08)
한글내용
(Korean Abstract)
영문내용
(English Abstract)
This paper describes a hardware-oriented algorithm and its conceptual implementation in
a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various
countries’ speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but highperformance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

키워드(Keyword) Advanced driver assistance systems (ADAS)   Speed limit traffic sign detection   Rectangle pattern matching   Circle detection   FPGA implementation  
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