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홈 홈 > 연구문헌 > 영문 논문지 > JSTS (Journal of Semiconductor Technology and Science)

JSTS (Journal of Semiconductor Technology and Science)

Current Result Document : 9 / 10

한글제목(Korean Title) Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance
영문제목(English Title) Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance
저자(Author) TaeYoon An   KyeongKeun Choe   Kee-Won Kwon   SoYoung Kim  
원문수록처(Citation) VOL 14 NO. 05 PP. 0525 ~ 0536 (2014. 10)
한글내용
(Korean Abstract)
영문내용
(English Abstract)
Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency (fT). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.



키워드(Keyword) Cutoff frequency   fin field-effect transistors (FinFETs)   fringe capacitance   number of gate fingers   number of fins   parasitic resistance   radio frequency (RF).  
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