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영문 논문지

홈 홈 > 연구문헌 > 영문 논문지 > JSTS (Journal of Semiconductor Technology and Science)

JSTS (Journal of Semiconductor Technology and Science)

Current Result Document : 1,196 / 1,197

한글제목(Korean Title) Energy-efficient Custom Topology-based Dynamic Voltage-frequency Island-enabled Network-on-chip Design
영문제목(English Title) Energy-efficient Custom Topology-based Dynamic Voltage-frequency Island-enabled Network-on-chip Design
저자(Author) Chang-Lin Li   Jae-Chern Yoo   Tae Hee Han  
원문수록처(Citation) VOL 18 NO. 03 PP. 0352 ~ 0359 (2018. 06)
한글내용
(Korean Abstract)
영문내용
(English Abstract)
The voltage-frequency island (VFI) design paradigm has strong potential for reducing energy consumption in network-on-chip (NoC). The V/F of each island can be dynamically tuned according to the application’s requirements. However, dynamic VFI (DVFI) requires an efficient on-chip communication architecture to compensate for the latency overhead produced while tuning the proper V/F of each VFI. Although standard topology has been used in most VFI designs, this approach incurs a large energy and latency overhead owing to the redundant hop counts. Therefore, we propose a custom topology-based DVFI for an energy-efficient manycore platform to maximize energy efficiency with a reasonable implementation cost. In this regard, a custom topology generation method with a heuristic run-time V/F tuning algorithm is incorporated by considering the core and link utilization. Experimental results demonstrated the effectiveness of the proposed scheme in terms of execution time and energy-delay product.

키워드(Keyword) Network-on-chip (NoC)   voltagefrequency island (VFI)   dynamic voltage-frequency island (DVFI)   custom topology   topology generation  
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