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영문 논문지

홈 홈 > 연구문헌 > 영문 논문지 > JSTS (Journal of Semiconductor Technology and Science)

JSTS (Journal of Semiconductor Technology and Science)

Current Result Document : 3,896 / 3,897

한글제목(Korean Title) Adaptive Multi-path BCH Decoder to Alleviate Hotspot-induced DRAM Bit Error Variation in 3D Heterogeneous Processor
영문제목(English Title) Adaptive Multi-path BCH Decoder to Alleviate Hotspot-induced DRAM Bit Error Variation in 3D Heterogeneous Processor
저자(Author) Prashanthi Metku   Ramu Seva   Kyung Ki Kim   Yong-Bin Kim   Minsu Choi                 
원문수록처(Citation) VOL 17 NO. 05 PP. 0717 ~ 0728 (2017. 10)
한글내용
(Korean Abstract)
영문내용
(English Abstract)
A 3D heterogeneous processor (commonly termed as 3DHP) integrates multiple processor (such as CPU/GPU) and DRAM dies, interconnected vertically by a massive number of Through-Silicon Vias (TSVs). The 3DHP is expected to address the limited bandwidth, high latency and energy consumption of off-chip DRAM. However, spatial and temporal variability due to hotspots in on-chip thermal gradient may result in wide bit error variation in DRAM dies. This work proposes a novel adaptive multi-path BCH decoder to efficiently address this issue. Instead of having a static BCH decoder designed from the worst-case bit error probability analysis, the proposed adaptive multipath BCH decoder offers multiple decoding paths with varying target number of error bits to correct, which is estimated from the thermal gradient data generated by on-chip temperature sensors. Thus, it minimizes the overall decoding latency adaptively. The proposed approach has been verified by implementing an adaptive 4-path BCH decoder in FPGA hardware. A series of decoding performance evaluation data has been generated to demonstrate the efficiency of the proposed design.
키워드(Keyword) BCH decoder   bit error rate variability   thermal integrity   3D heterogeneous processor                    
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